When a semiconductor device such as a metal-oxide-semiconductor field-effect transistor (MOSFET) is scaled down through various technology nodes, several strategies have been employed to improve device performance. One strategy is to use a high-k (HK) dielectric material and metal gate (MG) transistor. Another strategy is to use a strained substrate technology. For example, by implementing a strained substrate technology, better device performance is often achieved by modulating strain in a transistor channel, which enhances mobility (e.g., electron or hole mobility) and thereby conductivity through the channel. As an example, an epitaxy silicon germanium (SiGe), or silicon carbide (SiC) layer, is formed in source and drain regions in p-type FET devices, or n-type FET respectively. However, current techniques to form these strained structures have not been satisfactory in all respects. For example, these strained structures may not produce sufficient stress in a channel region to improve device performance.